The present invention relates generally to digital logical circuits and particularly to a digital system in which the propagation time delay of a digital signal or signals is critical with respect to separate logical elements within that digital system.
Digital systems, in particular digital computer systems, frequently need critically timed signals throughout the digital system. In digital systems in which the physical size of the system is small and which has relatively slow timing with respect to the speed of the circuits, the timing of signals being distributed through the digital system is not particularly critical. But as physical dimensions of the digital system become larger as, for example, the capacity of the digital system increases, the delay of certain timing systems signals becomes more critical as the propagation delay due to increased physical dimensions becomes greater and greater. Further, the margin for error in delay of timing signals decreases as the overall timing of the digital system becomes faster and faster with respect to the speed of the circuits involved. The physical delay in the signal routing of a digital signal throughout a digital system then may become a very significant factor. It may be intolerable, for example, to allow a given digital signal to reach a certain portion of the logic of the digital system substantially before that same digital signal reaches another portion of the logic located in a separate physical location from the other circuitry.
In many such digital systems in which the digital signals are critical, either the digital signals are adjusted manually or allowances are made in the logical design to enable the circuitry to tolerate the inherent propagation delays that these signals encounter. But many computer systems and other digital systems are constructed in a modular fashion in which certain logical circuits or elements may be removed from the system and the system may be constructed or reconstructed in a different modular fashion than before. This modular design tends to increase the physical separation between different logical elements within that digital system. Further, many digital systems have the option for a variety of circuitry functions which provide an additional variety of variance in signal routing and in circuit loading and in the use to which certain digital signals may be put. All these factors tend to increase the significance of propagation delays for certain digital signals within those systems.
Further, in critical digital systems, the delay of each signal is dependent upon the electrical loading, the number of circuits a particular circuit must drive, or is dependent upon the particular wire utilized or other transmission medium which is utilized and is dependent upon the exact routing of the transmission medium. Changes in any of these variables would necessarily change the propagation delay of a digital signal through that medium by changing such characteristics of the medium as the characteristic impedance of the medium or through inductive coupling into the medium as well as the time required to traverse a particular distance with an electronic signal. These differences may be different in different models of the same digital system or even in different units of the same system. Thus the delay to which a given digital signal may be delayed cannot accurately be predicted. Thus, unless some adjustment is made, an allowance must be designed into the digital circuitry to allow for variances in propagation delays. These allowances would necessarily decrease the overall speed of the digital speed of the digital system and hence are undesirable.
With the modular arrangement of digital systems, the predictability of propagation delays and the adjustment which must be made to compensate for these delays becomes very, very difficult.